Departments
- Editorial
  - Intel: Challenges of Leadership
    Have you ever been in a foot race?
- News
  - In the News
- Notable Developments
  - Optical Circuit Packaging Technology
    To serve a new seamless telecom and multimedia communications society, the smooth, fast, intelligent transmission and processing of large data files is necessary.
- Industry Voices
  - New Lead-free Processes Require Industry Collaboration
    The electronics industry is making steady progress toward developing lead-free assembly processes to meet the EU's Restriction on Hazardous Substances (RoHS) directive, which calls for the elimination of lead and other hazardous substances from new electrical and electronic equipment by July 2006.
- Packaging Trends
  - Overcoming Tin Whisker Problems on Lead-free Packaging
    The EU has set in place a Restriction of Hazardous Substances (RoHS) directive that states: "Member States shall ensure that from July 1, 2006, new electrical and electronic equipment put on the market does not contain lead (Pb), mercury, cadmium, hexavalent chromium, polybrominated biphenyls and polybrominated diphenyl ethers."
- New Products
  - New Products
- Editorial board
  - Applying Moore's Law to Wafer Test
    Gordon Moore's 1965 observation that the number of transistors per square inch of silicon was doubling every year has, with modest variations, continued to characterize growth in the semiconductor industry.
Features
- Cover Story
  - Next-generation Packaging Materials
    New developments in board/package materials and processes
- The Value of IC/Package/System Co-design
  Blending engineering knowledge across IC/OSAT/OEM companies
- Bond Testing Bumped Devices
  Test methodology considerations
- Variable Flip Chip Assembly for High-volume Production
  Solder bump and adhesive flip chip advantages
- The Back-end Process
  - Underfill Update, Step 6
    Materials and Processes

Editors' Picks

LIVE NEWS FEED

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Advanced Packaging Recent Articles

imec, PVA Tepla demo 3D TSV void detection

Novati to use Ziptronix bonding tech for 3D assembly

Through-wafer Inspection for MEMS Devices — a Comparison

EV Group and Brewer Science Establish Ultra-thin Wafer Bonding Lab

Gone Fishing

Localized Cooling for Data Centers

Solder-free Connectors Using Buckled Pillars

Packaging Topics

3D Integration

Wafer Level Packaging

Materials

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Table of Contents

Departments

Editorial

News

Notable Developments

Industry Voices

Packaging Trends

New Products

Editorial board

Features

Cover Story

The Back-end Process

Editors' Picks

Nanya implements 3D IC TSV technology for DDR3, future DDR4 devices

ASM Pacific Technology delivers 100 x 300mm leadframe packaging set up

3D TSV packages outgrow semiconductor industry by 10X

2012 ITRS update: Back-end packaging and MEMS

Roadmapping More than Moore: When the application matters

Contemporary semiconductor packaging experts open up on cost

TOP BLOG POSTS

LIVE NEWS FEED

Advanced Packaging Recent Articles

imec, PVA Tepla demo 3D TSV void detection

Novati to use Ziptronix bonding tech for 3D assembly

Through-wafer Inspection for MEMS Devices — a Comparison

EV Group and Brewer Science Establish Ultra-thin Wafer Bonding Lab

Gone Fishing

Localized Cooling for Data Centers

Solder-free Connectors Using Buckled Pillars

Packaging Topics

SUBSCRIBE

Issue 6

Table of Contents

Departments

Editorial

News

Notable Developments

Industry Voices

Packaging Trends

New Products

Editorial board

Features

Cover Story

The Back-end Process

Editors' Picks

TOP BLOG POSTS

LIVE NEWS FEED

Advanced Packaging Recent Articles

Packaging Topics

SUBSCRIBE