October 18, 2012 - SPTS Technologies has signed a joint development program with the Fraunhofer Institute for Reliability and Microintegration (Fraunhofer-Institut für Zuverlässigkeit und Mikrointegration, IZM) and its All Silicon System Integration Dresden (ASSID) center, to investigate sub-175°C dielectric films in through-silicon vias (TSV) for 3D IC packaging.

ASSID, created in 2010 to develop 300mm-based 3D integration technologies, will use 300mm plasma-enhanced chemical vapor deposition (PECVD) modules installed on a Versalis platform alongside SPTS etch chambers. Integrating the PECVD modules with etch processes on a single wafer handler will optimize process results and reduce capital expenditure for development and pilot production, the firms claim.

"SPTS has been an important partner, who contributes valuable experience and production experience for our 300mm 3D device stacking assembly line," stated M. Juergen Wolf, the manager of Fraunhofer IZM-ASSID and head of division HDI & WLP /ASSID. "The additional PECVD capability provided another important process step in this line." "We expect the advanced work Fraunhofer-IZM performed on our etch and PECVD process capabilities to accelerate the adoption of 3D packaging by volume manufacturers," added SPTS EVP/COO Kevin T. Crofton.

SPTS' advanced process module (APM) enables low-temperature PECVD for via-last applications and via-reveal passivation; depositing dielectric layers for TSV isolation at lower temperatures (<175°C) provides high sidewall coverage, low stress, and "in-via" electrical performance. For via reveal, the APM offers high deposition rate silicon oxide and nitride films compatible with silicon-on-glass substrates with what the company says are excellent coverage, barrier properties, and electrical isolation.

Via reveal occurs after the through-silicon vias (TSV) are formed -- wafers are temporarily bonded face-down to a carrier and thinned from the backside to reveal the vias, which are then passivated before final redistribution metallization. Temperatures at or exceeding 200°C can compromise temporary bond integrity. (Note that most fab processes typically run in excess of 300°C.) To this end, SPTS recently unveiled a new Delta fxP low-temperature PECVD cluster tool, with <190°C peak deposition temperature, for via-reveal passivation in 3D IC packaging.

PECVD via reveal. (Source: SPTS)