August 15, 2012 -- The Hybrid Memory Cube Consortium (HMCC), led by Micron Technology Inc. and Samsung Electronics Co. Ltd., released the initial draft of the Hybrid Memory Cube (HMC) interface specification, with the final version planned for end of 2012.
The industry specification will enable adopters to fully develop designs that leverage HMC’s innovative DRAM architecture, which combines high-speed logic process technology with a stack of through-silicon-via (TSV) bonded memory die.
The initial specification draft consists of an interface protocol and short-reach interconnection across physical layers (PHYs) targeted for high-performance networking, industrial, and test and measurement applications. The next step in development of the specification calls for the consortium’s adopters and developers to refine the specification and define an ultra short-reach PHY for applications requiring tightly coupled or close proximity memory support for FPGAs, ASICs and ASSPs.
“With the draft standard now available for final input and modification by adopter members, we’re excited to move one step closer to enabling the Hybrid Memory Cube and the latest generation of 28nm FPGAs to be easily integrated into high-performance systems,” said Rob Sturgill, architect, at Altera. The interface specification reflects a focused collaboration among several of the world’s leading technology providers. Micron and Samsung, the initial developing members of the HMCC, are working closely with Altera Corporation, ARM, HP, IBM, Microsoft Corporation, Open-Silicon Inc., SK Hynix Co., and Xilinx Inc.
HMC capabilities will leap beyond current and near-term memory architectures in the areas of performance, packaging and power efficiencies, offering a major shift from present memory technology.
One of the primary challenges facing the industry -- and a key motivation for forming the HMCC -- is that the memory bandwidth required by high-performance computers and next-generation networking equipment has increased beyond what conventional memory architectures can efficiently provide.
The term “memory wall” has been used to describe this challenge. Breaking through the memory wall requires an architecture such as HMC that can provide increased density and bandwidth with significantly lower power consumption. “As system designers face the simultaneous challenges of meeting exploding bandwidth requirements while staying within their power budgets, Xilinx is committed to technologies that allow them to address the bottlenecks in their systems while maintaining an acceptable level of power consumption,” said Hugh Durdan, VP, Portfolio & Solutions Marketing at Xilinx.
Adopter membership in the HMCC is available to any company interested in participating in development of the specification. The final interface specification is scheduled for completion and release by the end of 2012.
Additional information, technical support specifications and other tools for adopting the technology can be found at www.hybridmemorycube.org.