July 10, 2012 -- While the packaging industry tends to focus on advanced packaging -- processes at the wafer level, 3D integration, etc. -- the bulk of semiconductor packaging falls under the ‘contemporary’ category -- wire-bonded and flip chip designs. During the “Contemporary Packaging: Achieving Cost Advantage Through Innovation,” TechXPOT at SEMICON West, Dr. Sreenivasan (KK) Koduri, Texas Instruments (TI); Bob Chylak, Kulicke & Soffa Inc.; Leroy A. Christie, ASM Pacific Assembly Products; and Vinayak Pandey, STATS ChipPAC presented on themes like copper wire bonding and large-matrix leadframes. Presenter bios here: http://www.semiconwest.org/node/8511.
While some technologies offer a step change in cost improvement, most are more gradual reductions, said Koduri. Innovation can be applied outside of the package manufacturing equipment and materials, saving costs on financing, for example. R&D, Koduri noted, can add initial costs to the operation, but also find new ways to reduce costs. Quality control is a necessary cost; without strong quality control, packaging houses are being penny wise and pound foolish, he pointed out. Managing line logistics for high throughput, low downtime, and high capacity utilization are all ways to reduce spending before you even get into the package technology.
Getting into the technology of the package, Chylak focused on replacing gold (Au) bonding wire with copper (Cu). In addition to being a lower-cost raw material, Cu offers potential reliability and conductivity benefits over Au, if challenges with oxidation and bond pad damage can be overcome. At Kulicke & Soffa, the company designed its Cu wire bond tools with precisely placed gas jets that create an inert atmosphere. They take regular cross sections of bonds, which was not necessary with gold wire. Chylak also pointed out that packaging houses should ramp up copper wire bonding with a “middle step” between tool qualification and high-volume deployment. He recommends going from 1-2 copper wire bonders to 5-10 tools, allowing the packaging line engineers to understand the process and qualify various devices before installing the full load of tools.
The list of copper wire bond customers is growing: copper will be the dominant bonding wire material by 2015 (Chylak sources this data from Gartner), and Kulicke & Soffa’s installed base of tools is ~55% copper-bonding-enabled. More than 50% of the wire bonders at ASE use copper wire.
What else can we do with Cu? Cu stud bumps, bare Cu-to-Cu interconnects with unplated leadframes, copper wedge bonds to replace aluminum in power electronics/LED packaging, and vertical Cu wires used for through-mold vias of package-on-package (PoP) designs, Chylak says. So much for staying away from the advanced realm.
From wires to leadframes, Christie discussed the cost advantages of large matrix leadframes. Molding and singulation are ganged processes, unlike wire bonding. This means that the more packages go through the process at once, the higher throughput can be. Tip-to-tip (TTT) and interdigitated frame (IDF) leadframe designs are available to packaging houses. IDF can be more complex, but it offers more units/frame, and reduced unit pitch, Christie says. He also discussed the various shapes for mold flow (star, ll, and +) and their implications before getting into some case studies for large-matrix frames. When choosing a mold flow design, packaging houses need to take into consideration the effect on wires (wire sweep) as well as possible air gaps. Reformatting to large leadframes can cut costs at this step by 45% if yields are maintained. What’s next here? Christie says the company is working on 4-unit cascade mold fill, 100 x 300mm frames, possible support structures to avoid package damage during trim and form, and QFNs on large-matrix leadframes.
The final presenter changed the focus from wire bonding to flip chip packages. Pandey explained that the cost of flip chips primarily comes from the substrate, bump, and assembly. However, depending on the application, the cost distribution changes. For wired computing flip chips, for example, the majority of the cost is tied up in the substrate. Flip chips aimed for mobile applications have much less of the cost in the substrate, with assembly and bump combined making up 50%+ of the cost. Pandey introduced STATS ChipPAC’s concept of the cube flip chip (the company calls it fcCuBE) to reduce layer count in the substrate and use molded underfill (MUF) rather than capillary, and bond-on-lead interconnects rather than solder balls for lower cost without lower I/O density or reliability. As I/Os increase, the cost of a cube flip chip rises more slowly than the cost of a conventional flip chip does, Pandey said. In some applications, it is less expensive than a comparable Au-bonded package. The cube flip chip is assembled via mass reflow for most applications, which also keeps costs down. At leading-edge nodes (14nm/20nm), the package is assembled via thermo-compression bonding (TCB).
All of the presenters urged a holistic and constant approach to reducing cost. You cannot take the cost out of a flip chip once it is designed, warned Pandey. If you aren’t constantly innovating to reduce cost, Koduri said, you’ll probably see your costs go up.