June 7, 2012 -- Day 3 of the 15th IITC (International Interconnect Technology Conference) opened Wednesday, June 6 at the Doubletree Hotel in San Jose, CA under clear sunny skies and a pleasant breeze. The herd thinned a bit, down to ~150 hearty souls from the original 230 the prior two days.

Read Fury's reports from Day 1 and Day 2 of IITC.

Subramanian Iyer of IBM started the day with an invited talk on scaling in the 3^rd dimension (not to be confused with The Adventures of Buckaroo Banzai Across the 8^th Dimension) and prospects for silicon interposers and 3D integration. His retrospective introduction harkened back to IBM’s multi-layer ceramic thermal conduction module (TCM), which he re-characterized as an early model for today’s silicon interposers. A silicon interposer design with embedded decoupling capacitors has been shown to reduce the circuit-on voltage drop of a local net from 150mV to 20mV, with a significantly shorter time constant. 3D integration concepts have the potential to be implemented at smaller design units, from chip-to-chip today to the circuit-to-circuit level.

L. Peng of A*STAR (Singapore) described a 6µm pitch Cu-Cu bonding scheme for 3D wafer stacking. Cu-Cu bonding is favored because of its scalability and its ability to provide mechanical stability and electrical connectivity in a single mode. A self-assembled monolayer is used to protect the copper from oxidation and particle contamination during processing, and to ensure intimate contact of the copper surfaces. A surface roughness of 0.52nm is achieved with a dilute acid clean, comparable to a post-CMP roughness of 0.47nm. A pin density of 10⁶/cm² has been demonstrated with 6µm diameter and thermo-compression bonding (<1MPa) at 300°C for 30-60 minutes.

Figure 1. Qualitative comparison of enhancement methods: a) uniformly revealed daisy chain with Cu seal ring after Si removal; b) detached Cu bonding structures without Cu seal ring; c) zigzag Cu-Cu bonding interface with SAM enhancement; d) clear bonding interface due to presence of oxide without SAM passivation. SOURCE: A*STAR.

Fumihiro Inoue of IMEC showed a novel seed layer process using direct electroless Cu deposition on ALD-Ru for high AR (2µm diameter, AR 15) TSV. At 80nm thickness, the E/L Cu adhesion to Ru was high, and conductivity was adequate to serve as a seed layer.

Figure 2. Cross-sectional images of TSV after ELD-Cu. A) Whole SEM image; b) top TEM image; c) middle TEM image; d) bottom TEM image. The diameter is 2µm, and the AR is 15. ELD-Cu deposition time was 15 minutes. SOURCE: IMEC.

Arief Budiman of LANL used synchrotron XRD to compare mechanical stresses in Cu TSV samples from Hynix and SEMATECH. A microdiffraction technique was developed to characterize processes for optimization and line control. The samples were chosen to provide a range of dimensions to evaluate the metrology, not to compare the resulting devices. The TSV designs were: Hynix 20µm diameter, 90µm pitch, 90µm height; SEMATECH 5.5µm diameter, 80µm pitch, 50µm height. Cu hydrostatic stress, which is driven by Cu grain growth, is confirmed as the parameter that is most critical to optimize and control.

Figure 3a. Hynix’s TSV test structures: a) TSV array; b) X-ray fluorescence (XRF) mapping of TSV array; c) FIB image of as-received TSV sample and d) post-annealed sample.

Figure 3b. SEMATECH’s TSV test structures: a) XRF map of TSV array; b) FIB image of post-annealed TSV; and c) detailed XRF mapping of individual TSV. SOURCE: LANL.

Bill Taylor of GLOBALFOUNDIES gave an invited talk on BEOL challenges for 14nm and beyond. It’s getting hard to imagine how much more ‘beyond’ there can be. One model indicates that in moving from 20nm to 14nm, the line height will have to increase by 50% and the liner will need to change to Ta/Ru in order to maintain the same line resistance as we have at 20nm. Increasing height with the same line-line spacing requires increasing the etch angle, otherwise contact resistance at the line bottom is too great. LELELE and SADP can work at 14nm for patterning. Introducing multiple new materials in a single node change significantly increases the reliability risk for the technology.

Doug Ingerly of Intel described a low-κ 9LM interconnect stack with integrated MIM capacitors for high volume manufacturing at 22nm. The scheme provides a 15% average capacitance reduction with ULK CDO at lower layers (M1-M6) and 12% with CDO at the upper layers (M7-M9). A new high-κ HfO_x capacitor layer has been designed into the M8 dielectric (shown) that carries no real estate cost.

Figure 4. Transmission electron micrograph of Via-8, showing a MIM capacitor embedded in silicon nitride and sidewall connections to the electrode. SOURCE: GLOBALFOUNDRIES.

Masayoshi Tagami of Renesas (Albany) showed a 3LM 56nm pitch Cu/low-κ (2.7) interconnect scheme using sidewall image transfer (SIT) patterning with 193nm ArF. The SIT process is confirmed as “a strong candidate to achieve less R-C variation” for sub-50nm pitch nodes. Other processes considered were single exposure with EUV or multi-beam e-beam, and double exposure pitch split (LELE). The variation of the resulting 56nm pitch system is comparable to an 80nm baseline.

Figure 5. l/R-C plot for 56nm-pitched M2 line. SOURCE: Renesas.

Alan Myers of Intel Components Research demonstrated a 17nm half-pitch interconnect scheme using spacer-based pitch quartering. Demonstrations of 17nm with EUV showed that further work is needed to improve LER, among others. The quartering scheme results in 3 CD variation groups, shown as B, C, D in the figure. Extremely straight lines with no pattern collapse were achieved. Intel supports EUV. Backup plans are good.

Figure 6. Schematic of a pitch quartering flow using two spacer depositions. The sequential processing steps are labeled 1-6. SOURCE: Intel.

Alexander Hsing of Stanford U microprobed the mechanical effects on Cu bumps of varying dielectric porosity in advanced interconnect structures, in collaboration with GlobalFoundries. The mechanical test configuration is shown in the figure. The failure strength of the structure decreases with increasing porosity at 100°C and at 175°C; it also decreases with increasing temperature in this range. However, at 250°C the trend reverses and the failure strength increases with increasing porosity. This is believed due to a shift in the underlying failure mechanism from bump lifting from the die surface at lower temperatures to the bump shearing as it slides along the die surface at the higher temperature. Exposure of the dielectric stacks to 85% RH / 85°C by sawing into the stack causes a further 28% decrease in failure strength.

Figure 7. Full-depth (l) and half-depth (r) configuration of the microprobe metrology system. SOURCE: Stanford.

Linjun Cao of UT Austin analyzed grain structure of 45nm Cu interconnects with SiCN capping using precession electron diffraction to measure effects contributing to electromigration reliability, in collaboration with GLOBALFOUNDRIES. Spatial resolution was estimated to be 1-2nm. The technique was able to identify local critical flux divergence sites that are sources for void formation.

Figure 8a) Bright-field TEM image of the SiCN capped SG structure. Color-coded inverse pole figure orientation maps for the same structure along b) trench width and c) trench normal. Color codes for orientation are represented in the standard stereographic triangle. Texture is plotted along the trench width, trench normal, and trench length, respectively. SOURCE: UT Austin.

Franck Bana of STMicroelectronics (ST) developed an improved statistical analysis at low failure rates in Cu electromigration using an innovative multi-link test structure. Failure typically occurs near the cathode via, so the length of the narrow portion of the line was limited to 2µm to force a failure mode unique to the structure. Cu structures used a Ta/TaN liner with a SiCN top barrier.

Figure 9. Schematic layout of the multilink structure with N connected links in top view. SOURCE: STMicroelectronics.

Zsolt Tokei of IMEC described a novel miniaturized package for implantable electronic medical devices.  The device consists of a segment with a sensor element exposed to bodily fluids for insertion within the body near the organ of interest, connected via a variable length flexible interconnect to a second segment that is implanted subcutaneously. This near-surface segment contains the RF communication, driver electronics and battery for external connectivity. Particular attention is required to verify compatibility with all relevant bodily fluids and ensure no diffusion leakage of the electronics materials into the body. Extra passivation is required for SiN_x surfaces, as it has been found to be soluble in these environments. Cu interconnects are double passivated, first with Ta/TaN and then with Pt for stability in body fluids. While Ta and TaN are known to be biocompatible, there can be trace contaminants depending on the deposition parameters and precursor sources, making the Pt necessary.

Figure 10. Proposed miniaturized implantable packaging. 1) All chips are individually encapsulated by diffusion barriers using a wafer level process. 2) Biocompatible chip interconnections and embedding of multiple chips by a flexible polymer such as polyimide. 3) Final system assembly including biocompatible metallization and final embedding, preferably in a soft biomimetic polymer. SOURCE: IMEC.

Marleen van der Veen of IMEC talked about the electrical and structural characterization of 150nm AR 2.4 CNT contacts with Cu damascene top metallization. Contact resistance  was 2.8kΩ and breakdown currents were in the range of 5-13MA/cm². CNT were grown with a sputtered Ni catalyst and encapsulated with Al₂O₃; excess growth was planarized with CMP. Penetration of the CNT into the top metal TaN liner was confirmed with TEM on a cleaved sample. Scanning spreading resistance microscopy was used to show that each contact hold contained ~30 individual CNT channels.

Figure 11. Cross-section SEM of the 2 150mm CNT contact holes metalized with Cu damascene top contact module. SOURCE: IMEC.

Motonobu Sato of AIST (Japan) discussed his work on multi-layer graphene wires grown by annealing sputtered amorphous carbon. Replacing Cu with C is the overall strategy, with CNT for vertical vias and MLG, which can sustain current densities of 10⁷A/cm², for horizontal wires. Annealing in N₂ ranged from 200°C to 800°C for 30 minutes. The Co catalyst was necessary to drive 100% conversion to sp² graphene at 800°C. The Co was then removed in FeCl₂ solution followed by HCl. After Co removal, resistivity was ~500µΩcm.

Figure 12. MLG wire process. SOURCE: AIST.

The symposium concluded with Prof. Tetsu Tanaka of Tohoku U (Japan) delivering an invited talk on optical interconnect technology for 3D LSI and neural engineering. TSV is already passé, now giving way to through silicon photonic vias (TSPV). This design is contrasted with the through wafer interconnection (TWI) proposed by GA Tech. TPSV can be fabricated concurrently with TSV by leveraging the SiO₂ cladding that TSV already uses. TSV are filled with Cu, TSPV are filled with Si. Another essential element for system operation is a unidirectional optical coupler (UDOC) to redirect the vertical optical signal to a horizontal wave guide. A side and top mirror are proposed to box in the incoming light. Coupling efficiencies over 70% were achieved. Use of optical signals allows the extension of electronics technology from the “hard & dry” regime to the “soft & wet” world of living organisms. In some applications, optical stimulation of brain neurons is preferable to electrical stimulation. Integration of micro-fabricated optical fiber probes with electronic and chemical sensors allows the probing of precise brain locations with immediate detection of the local bio response.

Just under 100 people stayed for the talks right up to the closing bell. One hundred very exhausted people, all the more enlightened for the experience.

Michael A. Fury, Ph.D., Techcet Group, regularly blogs for Solid State Technology.