June 6, 2012 -- With many advanced packaging processes taking place on the semiconductor wafer, the traditional supply chain of front-end fab at the foundry and back-end fab at the packaging and test house is falling apart. Solid State Technology’s ConFab session, “Advanced Packaging and Progress in 3D Integration,” focused heavily on the new supply chain, or perhaps ecosystem is a better term, supporting advanced semiconductor packaging.
The supply chain faces a new reality, and new questions, said David McCann, senior director of technical business operations at GLOBALFOUNDRIES. How do packaging houses and IC designers determine the optimum locations for through silicon vias (TSVs) for power delivery and noise immunity when they are connecting stacks of die from different suppliers? How can cost be managed when multiple die per package are involved? GLOBALFOUNDRIES has installed TSV fab tools at its Fab 8 in NY, collaborating with tool makers and consortia.
|David McCann of GLOBALFOUNDRIES highlights the overlapping capabilities for advanced packaging in the supply chain.|
The old integrated device manufacturer (IDM) model of isolated teams and inflexible methods and systems doesn’t work with the fast-changing, highly complex world of advanced packaging. Neither does the current model of silicon customers interacting with the foundry and bump/package assembly and test companies individually. What is a working model? Supply chain alliances with intersections amongst tool suppliers, foundry and packaging companies and the silicon designers, aided by consortia. The supply chain cannot work if it is closed, and chipmakers must have the ability to choose suppliers based on their needs. McCann suggests co-locating to develop new tools, processes, and technologies for chips. No one company or organization can tackle all of the elements of advanced packaging development and production. Collaboration will help resolve technology challenges and set new designs up for high yields. Yield will define cost, which will determine success.
Sandeep Bharathi, VP of engineering at Xilinx, agreed. The capacity, bandwidth, and power benefits of implementing microbumps, die slices, and TSV in a stacked silicon interconnect packaging project were clear. What wasn’t clear was the supply chain to implement these processes. This was the hardest part of the project -- creating a new supply chain. The process is a chip making technology, and the fabless chip vendor owns the die stack.
Much work remains if 3D packaging can become mainstream. Not every semiconductor company can afford to piece together a unique custom design and fabrication process, as in this study, and this is where standards come in. Bharathi calls for fabless and fablite companies to align and collaborate with tool suppliers, fabs and packaging houses, and consortia.
If you want to integrate TSVs, you have a few paths laid out, said Ron Huemoeller, SVP of advanced interconnect platform development at Amkor. Keep the wafer at the foundry and perform back-end processing there, or send it to a semiconductor assembly and test services (SATS) provider for processing. Challenges in 3D assembly require expertise, Huemoeller said. And processes vary as well. Do you stack the die with chip on substrate, chip on wafer, or chip on chip assembly? As expected, each option offers pros and cons.
|Ron Huemoeller of Amkor lists the possible methods for stacking chips.|
Echoing John Chen of Nvidia’s opening keynote, William Chen of ASE’s presentation walked attendees through the changes from the days of the IDM that performed chip architecture design, semiconductor manufacturing, and package assembly and test to the current foundry/fabless/packaging house model where each owns one block of the process, and then to the virtual IDM model, which is evolving. The question to ask, Chen said, is if the IDM model is advantageous once we enter the complicated processes of 3D packaging. Virtual IDM concepts might answer.
|William Chen, ASE, shares the evolution of the packaging supply chain.|
Chen also took us from “front-end” and “back-end” processes to a term that’s been showing up in the semiconductor industry of late: “middle end.” Today, equipment & manufacturing processes for the middle end are to a large extent equipment & process from the front end adapted for the middle end, Chen said. Innovations and invention in assembly process and equipment productivity will be crucial to a new ecosystem.
Middle-end wafer processing takes a via-first TSV wafer with copper pillar bumps through thinning and dicing. In some cases the foundry will handle the wafer through middle-end processes, and in others the OSAT will. And of course, there will be captive models where start-to-finish fab takes place at the IDM.
For interposers, or 2.5D packaging, the possible ecosystem models are more numerous. Some will use foundries, interposer foundries, and OSATS with variations on what elements happen where; others will have the interposer made at the semiconductor foundry, again with variations in process ownership; and some IDMs will manage the whole process in-house.
Chen concluded with a look at some of the 3D and 2.5D packaging development efforts underway toward the goal of a complete ecosystem. Right now, the high level of interest in these ecosystems is the only agreed upon and decided thing.
Dig deeper into this ConFab session with 3D and 2.5D semiconductor packaging technologies @ The ConFab
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