June 26, 2012 -- Solid State Technology is hosting 3D and 2.5D Integration: A Status Report, airing live tomorrow at noon EST/9AM PST. The webcast is sponsored by EV Group (EVG) and ALLVIA, and is free for all attendees. This preview shares a sneak peek at “Markets for 2.5D and 3D TSV,” presented by E. Jan Vardaman, TechSearch International.
Vardaman will discuss the market for 3D ICs based on through silicon vias (TSV). There are cost/performance trade-offs for each possible application that will affect adoption. Some applications are using TSV packaging today, others are pushing TSV down their roadmaps.
Other alternatives -- interposers, package-on-package (PoP) stacks -- could delay moving to TSV integration. Design and test limitations are weighing heavily on TSV processes still. While TSV offers an ultra-compact and ultra-low-profile form factor, roadmaps could be shifting out farther into the future, for these and various other reasons.
Vardaman will look at several examples of 2.5D and 3D packaging architectures, from Altera to Xilinx.
E. Jan Vardaman is president and founder of TechSearch International Inc. and a published author. She served on the NSF-sponsored World Technology Evaluation Center study team involved in investigating electronics manufacturing in Asia and on the US mission to study manufacturing in China. She is a member of IEEE CPMT, SMTA, the Fabless Semiconductor Association, and SEMI.
Register here for the webcast: http://video.webcasts.com/events/pmny001/viewer/index.jsp?eventid=43122