June 6, 2012 -- The ConFab, taking place this week in Las Vegas, NV, is an invitation-only meeting of the semiconductor industry. As packaging has played a larger and larger role in chip performance, form factor, and capabilities, The ConFab has increased its focus on back-end processes. Cue “Advanced Packaging and Progress in 3D Integration,” a session chaired by Abe Yee, Nvidia, and featuring presentations from David McCann of GLOBALFOUNDRIES, Sandeep Bharathi of Xilinx, Ron Huemoeller of Amkor, and Bill Chen at Advanced Semiconductor Engineering Incorporated (ASE).
2.5D and 3D packaging are coming together to enable the end-goal of silicon devices -- high density, low power, low cost, high yield, small form factor heterogeneous silicon blocks integrated on one package.
|Ron Huemoeller of Amkor shared a look at systems in packages during The ConFab 2012.
McCann, senior director of technical business operations at GLOBALFOUNDRIES, spoke about advanced packaging and the technology challenges (and solutions) for leading-edge semiconductors. McCann pointed out the interconnection density increase enabled by advanced packaging, whether it be 2D like flip chip bumps (up to 10k I/Os per IC) or 3D like through silicon vias (TSV, up to 50k I/Os). Packaging must enable higher performance and lower power consumption, feeding a seemingly insatiable demand for video, Internet, etc.
|David McCann of GLOBALFOUNDRIES shares I/O density and package interconnect pitch trends.|
Insatiable bandwidth demand was the opening consideration of Bharathi’s presentation as well. Bharathi, VP of engineering at Xilinx, shared that there is a growing gap between number of logic gates and I/O in trying to meet bandwidth demand. There will be a 15x drop in I/O-to-logic ratio by 2020. Data demand was a hot topic at The ConFab 2012 -- read about it in articles on Semiconductor future and Big data.
McCann walked attendees through 2.5D packaging, which enables “fission” -- lower cost, higher yield, and smaller die than in competing solutions. It can scale each block independently, unlike a system on chip (SoC). It can also optimize power draw, benefiting the overall system.
Stacking silicon interconnects enables lower latency and power consumption in higher density than traditional I/Os, said Bharathi. The net result is 100X the die-to-die connectivity bandwidth per watt versus high-speed serial or standard parallel I/O. Monolithic die are limiting in capacity compared to “die slices” that can be ramped to high yields faster.
Bharathi explained Crossover SoCs -- new categories of devices that combine multiple functions on a single device with heterogeneous die made via different processes (CMOS, NMOS) and at different nodes (28nm, 65nm). The technical challenge here is that active die are stacked atop active die in a 3DIC, introducing thermal and mechanical stresses.
Bharathi’s presentation looked at a case study of stacked silicon interconnects in FPGAs at Xilinx, built on its proprietary ASMBL architecture, a modular structure comprising Xilinx FPGA building blocks in the form of tiles that implement key functionality such as configurable logic blocks (CLBs), block RAM, DSP slices, SelectIO interfaces, and serial transceivers. Xilinx engineers organize the blocks in columns of each type of tile and then combine the columns to create an FPGA. The device combines a 28nm active die and 65nm passive interposer. Microbumps and TSVs are implemented in a low-risk process, and the silicon interposer reduced stress with low-k materials. The benefits to capacity, bandwidth, and power were clear.
|A look at the FPGA, side view, that Xilinx's Bharathi discussed.|
Huemoeller, SVP of advanced interconnect platform development at Amkor, a semiconductor packaging and test service provider, zeroed in on TSVs.
TSVs can be used, as Bharathi said, to improve performance from 1 monolithic logic die to die slices, and will be used to segment monolithic analog/logic/cache functions onto separate die. Stacking die allows the silicon designers to focus process node developments on specific applications, reducing complexity and lithography mask layer counts. Wafer yield, in turn, goes up, and costs go down.
These benefits do not come at a form factor price. Quoting Samsung, Huemoeller said that TSVs interconnecting stacked die offer 8X better bandwidth and 50% power savings compared to package-on-package (PoP) memory.
Advanced package designs call for new materials and assembly and test methods at the wafer level. Smaller-pitch interconnect can increase the risk of warpage, for example. McCann pointed out that transistors and packaging are not 2 isolated silos. Copper-filled TSV interconnects add stress to the silicon. Thinning on transistors also must be characterized for potential impacts. Successfully addressing these issues will give chipmakers the benefits of shorter interconnects at higher densities, lowering power while increasing performance and bandwidth. On top of this, the wafer processing steps are complicated for advanced packaging, and known good die (KGD) testing is still developing, Bharathi added while discussing the new FPGA architecture.
2.5D interposers can be made from laminate, glass, or silicon. Laminate and glass suppliers are also eyeing this new market. Each material has its pros and cons. Laminates are limited to larger line/space pitch than package designs will require. Glass is available in several formats, but it can be very expensive to make vias in the material. Silicon interposer production is one option for idle legacy-node foundry lines, Huemoeller pointed out, except packaging lines want the interposers in 300mm formats. There are suppliers out there delivering fully functional silicon interposer wafers today. Expect >80% compound annual growth rate (CAGR) for 2.5D interposers through 2015 (300mm equivalent).
William Chen of ASE Group spoke in “Innovation & Collaboration in the 3D Ecosystem” at the session. The electronics industry is evolving from smart computing to ambient intelligence, another way to describe “Smart Society” or “Internet of Things.” With this comes a leap in electronics devices from 10+ billion to 100+ billion.
|William Chen, ASE, shared that ambient intelligence will require 100 billion electronic units, continuing the 10X+ multiplier path of electronics.
Over time, various advanced packaging methods, such as wafer-level packaging and die stacking and interposer interconnects, are converging. Parallel trends are emerging that use silicon interposers and 3D packaging with heterogeneous integration: for smartphones and other mobile computers, wafer-level chipscale packaging (WLCSP), flip chip CSP (FCCSP) and package on package (PoP) are converging; for networks and servers, ultra-low alpha, larger die, and larger packages are seen. Heterogeneous integration puts MEMS devices, memory, logic processors, and RF devices all on one substrate, in a small form factor.
At ASE, the packaging roadmap is transitioning from third generation -- flip chip, wafer-level packaging, and system in package (SiP) -- to fourth generation -- through silicon vias and wafer-level SiPs.
McCann’s packaging roadmap shows silicon interposers on the scene in 2011, memory cubes in 2013, logic and memory on interposers by 2014, wide-I/O memory in 2014, and heterogeneous stacking potentially in 2017.
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