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February 16, 2012 -- Georgia Tech’s Packaging Research Center (PRC) demonstrated a 3D organic package at 130µm thickness at 30µm interconnection pitch using ultra-short copper-copper (Cu-Cu) interconnections, chip-last integration, and bonding below 200°C.
The Ultra-SLIM Packages have built-in vertical connections to the top surface of the package for package-on-package (PoP) stacking using high-precision cavity embedding of thin silicon and gallium arsenide (GaAs) devices into ultra-thin organic modules with up to 1000 I/O routing capacity in 1-2 metal layers.
Various RF passive components have also been embedded into the substrate layers of the chip-last integration scheme. This allows packaging houses to perform intermediate testing after substrate fabrication and selective-site die embedding. Georgia Tech asserts that this form of yield management is superior to that available with fan-out wafer-level packaging (FOWLP) and chip-first embedding.
The first set of functional WLAN receiver modules fabricated using low-moisture and low-loss laminate materials from PRC industry partner Zeon Corporation was measured to meet all WLAN specifications in the 130µm-thickness form factor. Additional Georgia Tech PRC industry partners include Intel, Qualcomm, Infineon, Maxim and Namics.
Companies interested in this technology for RF, Power, Analog, MEMS/Sensors, and Mixed Signal Module Applications may contact Nitesh Kumbhat at nitesh.kumbhat@prc.gatech.edu, +1 404-385-0730 or Professor Rao Tummala at rao.tummala@prc.gatech.edu, +1 404-894-9097.
Georgia Tech recently hosted the inaugural Global Interposer Technology Workshop (GIT). Blogger Dr. Phil Garrou, Insights From The Leading Edge, attended and sent in these reports:
GIT 2012 will take place November 14-16 on Georgia Tech's campus. Learn more and submit a presentation abstract here.
Learn more about the 3D Systems Packaging Research Center at Georgia Institute of Technology at www.prc.gatech.edu.
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