July 6, 2011 - EV Group has joined Georgia Tech's 3D Systems Packaging Research Center (PRC) as a "manufacturing infrastructure member." Specifically, EVG will contribute its know-how and technology in temporary bonding and debonding, chip-to-wafer bonding and lithography technology, and associated product and processes to the PRC's Silicon and Glass Interposer Industry (SiGI) Consortium research program.
Launched earlier this spring, the SiGi Consortium is pursuing development of less expensive (up to 10× lower-cost) ultrathin glass interposers for routing electrical interconnections vs. wafer-based silicon interposers.
"The company's advanced, production-proven equipment and comprehensive process know-how will enable EVG to greatly contribute to our pioneering system-on-package technology research and development," stated PRC Director Professor Rao R. Tummala. (He was recently recognized with the IEEE's major Field Award for his seminal contributions to microelectronics packaging.)
"Through membership in and collaboration with the PRC, we aim to further develop technologies that will make silicon and glass interposers with TSVs a truly affordable packaging solution," noted Paul Lindner, EVG’s executive technology director, in a statement. EVG was a cofounder of the EMC-3D consortium back in 2006 to address the technical and cost issues of creating 3D interconnects using through-silicon vias (TSV) for chip stacking and MEMS/sensors packaging; that group, having met its goal of $150/wafer, will be ending this summer.
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