December 30, 2011 -- As the semiconductor industry moves into the 22nm silicon technology node, device fabrication is not the only challenge that the industry will face. According to the International Technology Roadmap for Semiconductors (ITRS), a porous ultra-low-k (ULK) material will replace the traditional silicon dioxide. Stresses within the die must be controlled, not only during wafer fabrication, but also in packaging and assembly.

This will be even more challenging than the industry’s first adoption of early low-k materials. Foundries forgot to mention the change in the device structure to the assembly houses. As a result of stresses from the materials used and the assembly process, delamination occurred within the die itself. The result was a lot of devices that had to be scrapped and semiconductor companies missed revenue targets. Assembly houses had to modify wire-bonding processes and even make changes to molding compounds. For devices that were flip chip bonded, underfill materials had to be modified.

At the 22nm technology node, the devices may be even more fragile, requiring further material changes. Many of these devices will likely use flip chip interconnect with a lead-free solder bump, compounding the problem further. Co-design of silicon and package will be essential. New material formulations will be required, especially for underfill. Potentially, packaging houses will need to change the assembly process itself. Even the package structure may require change.

Silicon interposers have already been found to be helpful in handling stresses that could impact the fragile device layers at the 28nm technology node. As Xilinx began its first shipments of its Virtex-7 2000T field programmable gate array (FPGA) using a silicon interposer, the company found that a side benefit of the use of the interposer was the fact that it helped mange the stress in the packages between the die and the laminate substrate. Assuming the supplier infrastructure is well established, a number of companies may opt for silicon interposers to improve package reliability. Xilinx’s part is unique in that the die are partitioned into four slices that are mounted on a 65nm node passive silicon interposer with 10:1 aspect ratio through silicon vias (TSV). The interposer has four interconnect layers on each side. The slices are mounted on the interposer with copper pillar microbumps and chip-to-chip communication is through the interposer. Co-design with new packaging technology resulted in a new FPGA that allows reduced system cost and increased performance in a high-bandwidth, low-latency, power-efficient interconnect solution. The silicon interposer solution may be the answer for mobile devices as well as high-performance applications such as servers and network systems.

Another option that may see greater adoption at the 22nm technology node is some form of 3D stacking of memory and logic with TSVs. 3D TSV is often touted as the way to achieve higher bandwidth, greater performance and lower power, but business and infrastructure logistics must be worked out.

Whatever package structure is adopted, this new era of silicon device technology will require greater use of co-design and much closer cooperation between IC designers, foundries, and assembly partners. In-package integration will provide major advantages for devices makers through the next-generation silicon technology.

E. Jan Vardaman is president and founder of TechSearch International.

This article is part 5 of a series of 22nm forecasts from Solid State Technology contributors.

Part 1: Semiconductor process technology challenges at 22nm by Dean Freeman, Gartner

Part 2: At 22nm, leave chip layout to the experts by Gary Smith, Gary Smith EDA

Part 3: Focus on first order effects at 22nm by Howard Ko, Synopsys

Part 4: Mask-wafer double simulation: A new lithography requirement at 22nm by Aki Fujimura, D2S

Part 6: Strained silicon and HKMG take the stage at 22nm by Mohith Verghese, ASM America

Part 7: Will 22nm need a mid-node? by Art Zafiropoulo, Ultratech

Part 8: Startups pave the way to CMP at 22nm by Michael A. Fury, Techcet Group

Part 9: 20nm mask technology relies on SMO and DPT by Franklin Kalk, Toppan Photomasks

Part 10: 3D integration key to 22nm semiconductor devices by Paul Lindner, EV Group