November 28, 2011 -- Leti’s recent work includes nanophotonics communications devices, which use 3D chip interconnect. ElectroIQ.com caught up with Hughes Metras, director, North America, for Leti, at the IEEE San Francisco Bay Area Nanotechnology Council half-day symposium (11/15/11, Santa Clara, CA). Metras presented a paper on “Nanophotonics communications and 3D integration on CMOS interconnect.” He summarized some of Leti’s work in a podcast interview.



Metras said that the heterogeneous integration of photonics on silicon by direct bonding is the best compromise among performance, functionality, and manufacturability to achieve a laser on silicon. And though III-V compounds are very difficult to grow on silicon material, they offer good performance in terms of power, light source, and wavelength. So Leti had to find a way to rapidly put these devices on top of waveguides where the light is conducted and at the same time avoid the difficulties of CTE mismatches and crystallographic mismatches. “We can bond a die that has been roughly prepared with only the active layers,” explained Metras. “And the engineering of the cavity is done after the bonding process, so you don’t need a very accurate pick and place process, you just do the cavity definition through the lithographic process.”

With respect to bonding processes needed for photonics on silicon, Leti is investigating both wafer-to-wafer and die-to-wafer bonding; the technology used will depend on the application. “We believe die-to-wafer will be first to market and we are working with development teams (i.e., equipment suppliers) to increase the pick and place process for this technology,” said Metras.

Wafer-to-wafer bonding requires more accuracy at the full-wafer level in terms of defects, regularity of the features noted Metras. It’s also a good solution for very high-density interconnections, but requires more post-processing to ensure the Cu-Cu interconnects heal after the process. By contrast, “the die-to-wafer bonding process is easier to set up and it’s good for some applications, but requires some techniques of handling the die that are less productive. And sometimes dealing with small die is very difficult in terms of fast production techniques.”  

Summarizing Leti’s photonics on silicon roadmap, Metras said the consortium is starting to do some development with partners (e.g., Alcatel). In two years Leti expects to develop a 25Gb/sec connection. “And 3-4 years from now, we’ll aim for a 40Gb/s link,” said Metras. “Within the next 5-10yrs we would like to do a first demonstration of a silicon-on-chip interconnect.”

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