September 23, 2011 -- Research and Markets released "Wafer Packaging Fab Database," providing a global overview over 150 companies' 250+ mid-end semiconductor packaging houses. Small R&D and prototype lines are also listed. Data includes wafer-level packaging (WLP) activity and installed capacities.
Flip chip wafer bumping and wafer-level chipscale packaging (WLCSP) make up the mainstream of WLP. On the leading edge are through silicon via (TSV) for 3D WLP, 2.5D interposers, fan-out WLP (FOWLP) and other technologies that require new capacities and capabilities.
The database references more than 250 fab locations worldwide with technical information on wafer bumping, re-distributed layers (RDL), passivation, through-silicon via (TSV), and "mid-end" capabilities, and wafer-level packaing capabilities in general.
The database targets equipment & material suppliers looking for customer opportunities, fabless/fab-lite semiconductor companies looking to outsource, and other users.
WLP technologies distribution can be sorted by players, technology type, country, business model, investment & growth evaluation. Users can view the companies performing a certain packaging technology, and study players manufacturing/outsourcing strategy and supply chain. Others can identify and source new WLP service suppliers for their wafer-scale packaging needs. 20+ graphs are included to illustrate global trends.
|Sample of companies listed in the database (IDMs, OSAT, foundries, MEMS, R&D Lab, etc.)|
|Wafer bumping houses:
|Wafer packaging houses:
|R&D Lab & prototype lines:
|MEMS IDM/foundries: Silex
|IC manufacturers (IDM):
For more information, visit