September 7, 2011 - 3M and IBM say they are jointly developing a new class of material adhesives specifically for stacking and packaging semiconductors in layers of up to 100 separate chips. The resulting silicon "brick" could make chips 1000× faster than today's fastest microprocessor.
Today's chips, even those touted as "3D" transistors, are really just flat-structure 2D chips, claims IBM's Bernie Meyerson, VP of research. These new materials, though, would enable a new formfactor of "a silicon 'skyscraper'" and a new class of semiconductors that support faster speeds and capabilities as well as lower power usage -- key considerations for apps such as tablets and smartphones, he said in a statement.
The work, which they say "can potentially leapfrog" current industry efforts at vertically stacking chips (i.e. 3D packaging), centers on a new type of electronic "glue" that connects up to 100 separate chips, while conducting heat away from the silicon package. The adhesive will be applied to silicon wafers to coat the chips themselves, hundreds or thousands at a time, which they compare to packaging/bonding techniques applied to single chips. The adhesives also will conduct heat through the dense chip stacks but away from components such as logic circuits. The JV work will draw on IBM's semiconductor packaging process expertise and 3M's adhesive materials development/manufacturing know-how.
IBM offers a video of how the new adhesives would work, sandwiching gobs of "heat-dissipating adhesive" in between multiple chip layers to create the silicon "brick." The photo below shows a stillshot from that video. We'll update this story as we get clarification as to how the adhesives & stacking process would technically be achieved, and how obvious obstacles would be overcome -- e.g. safely and efficiently dissipating heat from in between dozens of stacked chips.
The glue (shown in blue) connects up to 100 separate chips as it conducts heat away from the silicon package. (Source: IBM)
Update 9/9: We checked with a trio of industry analysts for some thoughts on how this IBM/3M work might take shape:
Dr. Phil Garrou, contributing editor, Advanced Packaging: These are high thermal conductivity underfills. Little to no information being shared on the roadmap, desired specs, or applications. But the announcement appears to be driven more by 3M. [Dr. Garrou will have more info forthcoming on his blog, Insights from the Leading Edge.]
Jim Walker, Gartner: This seems to be a new material to relieve thermal dissipation that will come with using TSV interconnects and wafer/die stacking. No details about the chemistry composition of the 3M material, but presumably it's polymeric -- if it was some type of glass, Corning would be the more likely partner.
Dean Freeman, Gartner: It basically sounds like a bonding polymer that takes heat out of the device. This might allow for stacking of several logic devices in the same package -- e.g. multicore stacked on multicore, a server on steroids. Stacking the CPU on top of each other eliminates PCB wiring, and eliminating external interconnect would possibly save power, and result in a faster system. Getting the heat out is a challenge; can you package these devices together successfully? Bonding entire wafers with reasonable yield is a big challenge.