by Michael A. Fury, Techcet Group

June 20, 2011 - Seventy attendees comprised the standing room only crowd at SEMI's HQ for the special June 15 NCCAVS user group meeting on 3D Packaging, co-hosted by three of the Bay Area User Groups: CMP, Plasma Applications, and Thin Film. The presentations will be posted on one or more of these groups at http://www.avsusergroups.org/ as soon as they are available.

Rob Rhoades, CTO of Entrepix, led off the session with a review of CMP issues unique to through-silicon vias (TSV). Copper is the prevalent choice for TSV metal fill, being used 2×-3× as often as all other choices combined -- though it surprised me a bit that its selection was not much greater than 2×-3×. Polysilicon via fill is second most common. In a distant third place are a group of materials chosen for specialized applications and specific process demands, including Pt, W, NiFe, and NiFeCo. CMP slurries for these materials are available only through trial and error with existing commercial products, eventually leading to collaboration with the slurry supplier if the market opportunity warrants. Most TSV process flows require only one CMP step, though some require two, usually for different materials. Entrepix has become a reasonably prolific resource for developing CMP processes and consumable sets for applications and materials outside of the CMOS mainstream.

Deepak Sekar, chief scientist at Monolithic 3D, talked about their application of multilayer memory structures on a single chip to increase bit density by 3.3× using the same number of litho steps as a comparable 1× structure in a floating body DRAM architecture. Alternating layers of SiO₂ and patterned doped Si as thin as 50nm combined are stacked using an SOI-like cleave method, then etched together with a single mask before a common gate structure is deposited on top and spanning the sidewalls. His strategic roadmap calls for evolving a 22nm standard 2D device to a 2-layer 3D device, and subsequently to a 4-layer device, thus extending the 22nm litho and process tool set for six years or more over a conventional roadmap.

Valeriy Sukharev, a lead scientist at Mentor Graphics, talked about a DFM methodology that bridges the dimensional gaps between chip-scale and package-scale stress-induced effects in 3D TSV packaging designs. The method -- developed to address the failures in both finite element analysis and empirical modeling that have plagued engineering simulations of these types of structures -- is calibrated by fitting simulation data to measured stress and electrical data. A wealth of related information on TSV interconnect stress management can be found online at SEMATECH's Wiki page.

Sesh Ramaswami, senior director at Applied Materials, gave a high-level overview of TSV process integration challenges with a comparison of the process flows of via first, via middle, and via last, all using copper fill. The presentation contained a wealth of process detail on all of the process options, with a common theme demanding co-optimization of etch, CVD, PVD, ECD, CMP, bonding, and thinning for wafer front-side and back-side processing. He predicts that TSVs will start to show up in high-volume manufacturing in 2012.

I also attended the NCCAVS CMPUG regular meeting on May 18, but managed to procrastinate my blog report into obsolescence. The presentations are already available online, so readers can self-blog at their leisure.

Michael A. Fury, Ph.D, is senior technology analyst at Techcet Group, LLC, P.O. Box 29, Del Mar, CA 92014; e-mail mfury@techcet.com.