By Debra Vogler, senior technical editor
March 30, 2011 -- In a podcast interview recorded after SEMATECH’s workshop on design for reliability, stress management for 3D ICs using TSVs (3/17/11; Santa Clara, CA), Larry Smith, manager of SEMATECH’s 3D Enablement Center, summarizes the presentations and findings at the event. "Management of mechanical stresses is one of the key enablers for the successful implementation of 3D integrated circuits using through-silicon vias (TSVs)," Smith told ElectroIQ. "Copper-filled TSVs and wafers thinned to a few tens of microns modify the stress profiles in the silicon, and may exacerbate the stresses introduced by tier-to-tier bonding and chip-package interactions." Because these stresses have the potential to modify device characteristics, they could affect functional and parametric yield and reliability. "The stress-related impact of the processing done at the various companies in the manufacturing supply chain needs to be characterized and shared, and designers need a DFM-like solution for managing stress." Also read: TSV can deal with stress, says Synopsys
Not all efforts are directed at process challenges, however; much attention is directed at business challenges. "Concern revolves around which entity will be doing the 3D portion of a manufacturing process: the foundry, the OSAT, or the memory supplier," explained Smith. "Depending on where it gets done, that changes the critical interfaces and the standards that will be needed." Furthermore, ownership of any bad parts has to be resolved.
Smith noted that it’s commonly recognized that there is not yet a lot of manufacturing experience with respect to 3D, so the industry as a whole does not have a lot of confidence on prioritizing the failure mechanisms. "Copper pumping, or extrusions, are a concern with TSVs, and though there have been presentations with solutions," said Smith, "there is still concern as to whether or not all the issues are truly understood and really solved." Some of those outstanding issues include integrity of the liner and barrier around a TSV, along with delamination at the interfaces. A second major issue is the use of very thin die and the stresses that come with micro bumping, and so forth. And there are still questions with respect to warpage, coplanarity, and die strength. Smith further commented that while some have talked about optimizing the copper plating process and annealing, little in the way of specifics have been revealed.
"The application that the industry is focusing on now [for high-volume manufacturing (HVM)] is wide I/O DRAM for mobile applications," said Smith. "The timeline for this to be ready for HVM is by the end of 2013." He thinks it’s a good application driver for 3D; yet another application for 3D is combining processor and memory for high-performance servers. "Right now, the real need is for standards (design and modeling and EDA tools, equipment, handling, inspection/metrology, reliability test methods, etc.)." Standards will be tackled by SEMATECH’s 3D Enablement Center.
In the podcast interview, Smith also discussed accomplishments with respect to modeling -- linking last year’s workshop (in total, there have been four SEMATECH workshops about this topic) with this year’s presentations.
1) Consensus on the methodology and approach (classic FEA for packaging, SNPS FEA for feature level modeling, and compact model for chip level modeling);
2) Consensus for material characteristics required;
3) Consensus for characterization techniques required for the material characteristics;
4) Several teams are considering how to interface some of the modeling tools; and
5) In terms of behavior, a compact modeling approach verified vs. classic FEA.