by Dr. Phil Garrou, contributing editor
February 27, 2011 - Samsung -- who in December 2010 announced 40nm 8GB RDIMM based on 4Gb, 1.5V, 40nm DDR3 memory chips operating at 1,333MHz and 3D TSV chip stacking architecture for servers applications -- announced at the International Solid-State Circuits Conference (ISSCC, Feb. 20-24 in San Francisco) the development of wide I/O 1Gb DRAM for mobile applications like smartphones and tablet computers. The 3D TSV architecture will be implemented in their 50nm node DRAM technology.
Previous generations of mobile DRAM, low-power DDR2 DRAM (LPDDR2) which runs at approximately 3.2-Gb/ sec, uses a maximum of 32 pins for I/O. The new wide I/O solution, which has 512 I/O (up to 1200 total pins), can transmit data at a rate of 12.8Gb/sec, resulting in a significant improvement in processing power. In addition it reportedly reduces the power consumption by 75%.
Following this wide I/O DRAM launch, Samsung is reportedly focusing on 20nm, 4Gb wide I/O mobile DRAM for delivery in 2013.
The 64.34mm2 is made up of 4 partitions symmetric with respect to the chip center, each partition consisting of 4×64Mb arrays, peripheral circuits and microbumps. The microbumps are 20×17μm2 on 50μm pitch. The TSVs are 7.5μm diameter with 0.22 - 0.24Ω resistance and 47.4fF capacitance.
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