by James Montgomery, news editor

October 12, 2010 - Traditional lithography-enabled scaling has partly given way to materials integration (e.g. strained silicon and high-k/metal gates [HKMG]), and now we're now entering the new world of 3D-enabled solutions such as density, FinFETs, and package integration, proclaimed David Bennett, VP of alliances for GlobalFoundries, at a recent SEMI-hosted seminar at the U. of Albany College of Nanoscale Science and Engineering (CNSE).

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Bennett exhorted that integrating frontend and backend (packaging) manufacturing will be "a given" below 28nm. (GlobalFoundries has bump capabilities in Dresden but he said it's not clear if those will stay there, or maybe move to NY.) A lite version of integration (he called it "1.5D") will be implemented at 28nm/22nm, but true 3D integration of memory and logic won't be seen until 2014, he said. Stacked die through-silicon vias (TSV) are in unit development now, but there are concerns about thermal and power management that "back way up into the supply chain," he said. Right now the best case for TSV is "good die" (vs. known-good die) -- a 90% yield of 90% yield is "not economically viable."

Bill Taylor, program manager for SEMATECH's frontend process integration and characterization, agreed that 3D interconnects are an "industry game-changer" for emerging system-on-chip application, with diverse approaches e.g. chip-to-chip or wafer-to-wafer -- i.e. one "monster" via or lots of smaller ones. Industry success depends greatly upon, and is delayed by a lack of, convergence of infrastructure and standards, he said. Tool and materials infrastructure is still "immature," he said, with numerous technology options and process flows, and several key tools have "extremely low productivity." Gaps in the supply chain must be filled, too, he said, such as partitioning new processes and developing standards to permit chips from multiple suppliers to work together.

CNSE recently won a competitive regional race to house a new 3D integration and packaging center, initially a $50-$100M investment, including support from the state, with future stages bumping this to >$100M. This will incorporate work on high-bandwidth memory on a logic processor, as well as MEMS integration and "sensorization," said Michael Liehr, AVP for business/alliances/consortia at CNSE. Prototyping in this center is expected in 2011, with a 300mm toolset and cooperation with an unnamed MEMS foundry. In a subsequent conversation with SST, Liehr dashed any imagery of a new "center" implied as gleaming new cleanrooms and facilities -- this new work is actually spread out in CNSE's existing North and Central buildings, mainly in SEMATECH's labs. New tools are being ordered, with development work expected to initiate in 2Q11. Stages 2 and 3 will expand work into areas such as C4, microBGAs, and laminates, but Liehr said it's not yet decided which will come first.