by James Montgomery, news editor

July 26, 2010 - There was a great deal of buzz at SEMICON West about 3D ICs, thanks to down-the-street ASMC presentations and backend discussions and vendors present. Through-silicon vias (TSVs) in particular are a hot ticket -- so much so that traditional frontend equipment suppliers are touting their entry. (Novellus, for example, made a splash with a suite of tools for wafer-level packaging dubbed "The New Vertical Reality," staking claim to what it says is a $700M+ market.)

(Phil Garrou also summed up several 3D/TSV presentations from SEMICON West: the TechXspot session on "Bridging the Gap," and Suss Microtec's "3D IC Bonding and Thinned Wafer Handling Workshop.")

There are more than 15 300mm 3D IC pilot lines now, according to SEMI's Jonathan Davis, priming the Tuesday Executive Panel's discussion about 3D ICs. Lam's Steve Newberry predicted the industry will see widespread adoption in 4-5 years (maybe 2-3), though standards are needed to more efficiently implement it -- e.g. will it be via-first, via-last, something else? It's also a relatively small market (a "niche" for etch, in LRCX's view), so ROI will be tough to justify for some, and few players will be able to pay for the R&D. AMAT's Thakur takes a broader view of 3D IC opportunities, emphasizing formfactors and performance. GlobalFoundries' Tom Sonderman likened TSV adoption to that projected for EUV lithography, requiring collaboration and a need to identify value-adds.

3D and TSV offer attractive growth, but there are still questions and hype to resolve. "While front-end semicap companies were very bullish on TSV, some back-end contacts wondered aloud how TSV will reach meaningful volumes soon as some critical standards are still not formulated," writes Credit Suisse's Satya Kumar. Citing the challenge of getting market penetration with "more capable, but also more expensive tool sets, to an end market that has traditionally used low-end, very low-cost tools," Deutsche Bank's Steve O'Rourke projects adoption of TSVs will start in traditional wafer fabs first, then "potentially" move to backend fabs, with prices lower -- "but not by much" than traditional frontend tools. Winning strategies will present "a combination of capabilities and cost of ownership arguments," he writes -- but "we maintain healthy skepticism on timing and market size expectations."

Though efficiency can offer a valuable proposition, it's hard to overstate how hugely important are costs (low) and availability (now) to backend customers. Several people with whom we talked at SEMICON West about how traditionally more frontend-oriented tool suppliers are clamoring for growth in packaging suggested it might be a tough sell, especially at the subcon level. One industry watcher said that OSATs have a simple interface point for these folks: ask them about lead-times, and if the answer is anything more than three weeks the conversation's abruptly over. Another pointed out that in many cases, backend outsourced firms translate "lead-time" as the time it takes to walk to the dock, unwrap the plastic from one of a long bank of tools already sitting around, and plug it in.

TI's Cu pillars

Packaging wasn't just a hot topic among suppliers. Texas Instruments made a splash with partner Amkor, announcing qualification and production of a fine-pitch Cu pillar flip-chip package -- <50μm, vs. ~150μm pitch size limitations with conventional solder-based flip chip, e.g. ball bond.

Cu pillars offer advantages over conventional solder in terms of thermal performance, better conductivity, and resistance to electromigration, as well as shorter package routing (higher pin densities, reduced die sizes). The industry is investigating their use for various reasons, e.g. as an alternative to wafer-level packages for analog devices, or replacing gold wire in some packages. Intel uses Cu pillars in its 65nm and 45nm flip-chip products (and is expected to continue through 32nm).

TI executives explained the technology is ideal for applications ranging from ASSPs (smaller body size, high pin count, low-power aspects) to DSPs (same requirements), and power management (density more than pin count) -- and they've got customers already lined up in all three product areas. "We looked at least two other alternatives" besides Cu pillars, and "we actually built products on them, they worked fine," noted Devan Iyer, TI's manager of worldwide semiconductor packaging. "But on the long-term roadmap, we feel like Cu pillar is the most cost-effective, the most standard in the industry."

The TI/Amkor announcement "represents one of the major adoptions outside of Intel and I believe it is the start of the wave," Jan Vardaman, president/founder of TechSearch, told SST, in conversations during and after SEMICON West. She added that she sought out the first major product known to employ the Cu pillars, a hot-selling smartphone (whose backer rhymes with "Frugal") -- but found it to be sold out in the wireless provider's store, despite a stated retail price north of $600 (without a contract).