By Bernie Siegal, Thermal Engineering Associates, Inc.
A thermal test chip is usually designed to help thermal engineers answer critical thermal packaging or material questions. These chips can be divided into to basic groups one for general purpose applications and the other for thermal simulation of a very specific application chip. The former group is used for package characterization in standard or application-specific thermal environments, heat sources in multi-chip packages (MCMs), and system-level thermal studies. The latter group targets specific chip designs that have complex heat generation topologies such as multi-core processors or system-on-a-chip designs and are designed on a one-for-one basis. Thermal test chips for the latter group are usually designed by the manufacturer of the corresponding application chip as a tool to help their customers get started on the thermal design efforts well before the application chip design and fabrication is done.
The general-purpose thermal test chip must meet the following key requirements:
This paper describes a thermal test chip that meets these requirements in the simplest manner possible. It has a standard heat source with integrated temperature sensors in a format that can handle both wire bond and bump chip configurations in a scaleable array size. This allows a single wafer to supply various array sizes to meet changing requirements.
The thermal test chip described herein is based on a unit cell that has two resistors and four diode temperature sensors in each cell (Figure 1). The resistors are deposited metal film resistors that have resistance values suitable for laboratory measurements. Each resistor is 7.6Ω nominal, a value chosen to better realize a wide power dissipation range using normally available laboratory power supplies. The two resistors are laid out to occupy 86% of the available area within the electrical contact pads, thus conforming to the JESD51-41 85% coverage requirement; the resistor layout is shown in Figure 2. Note that each resistor has two contacts at each end. One contact at each end is used for the power connection while the other is used for measurement; this 4-wire Kelvin Connection eliminates contact resistance problems during voltage measurements across the resistor. The metal film resistors offer better resistance uniformity a (typically ≤±5%) cross the wafer and ≤±2% across a 4×4 array of cells and also have low-resistance temperature coefficient values. This attribute results in relatively constant power dissipation over the course of thermal measurements. The designed current handing of each resistor, connection trace, and pad is 1A, allowing the 7.6Ω resistor to dissipate >7W each.
The four temperature sensing diodes are strategically placed at the center, two diagonals and a center edge, as shown in Figure 2. These four locations re-present the usual areas of concern when making thermal measurements and are replicated in an array so that there is always a center, two diagonals and a center edge temperature sensor in an array no matter how the array is laid out. The characteristics of the diodes are such that a precision 1mA current source will produce a nominal 0.7V across the diode at TJ = 25°C. The relationship between VF and TJ is well known and, with calibration, the diode makes an accurate temperature sensor. Each diode is connected to a conductive metal line that runs from one edge of the cell to the opposite edge. This allows Measurement Current (IM) to be applied to two edges of the cell while Forward Voltage (VF) measurements are made using separate contacts on the two other edges of the cell.
For a thermal test chip to be useful in package thermal characterization efforts, the chip size must closely approximate the size of the various application chips that willbe used in that package. However, given the development and fabrication expenses and the development time, it is not economically feasible to create many specific size thermal test chips. The array approach offers the possibility of combining many unit cells in various manners that better approximate the application chip sizes.
The problem in using arrayed wire-bonded unit cells is that inter-cell wire bonding is necessary to access all the cells. This makes package assembly and use somewhat problematic and relatively expensive. The solution to this problem is to make the connection metallization in the cell extend beyond the cell boundaries to the next cell. Then when the test chip wafer is cut into the desired array configuration, the inter-cell connections are already in place. Cutting up the wafer requires a two-pass operation one pass to remove the metallization in the cut area, and a second pass to actually cut the wafer.
Figure 3 shows a small 3×3 (approx. 7.7X7.7mm) array. Note that in this configuration there are six parallel series strings; these strings are electrically isolated from each other allowing them to be connected in parallel for uniform heating or for individually powered series strings for non-uniform heating. Each series string has a power connection pad and measurement connection pad on the array periphery, which makes wire bonding easy.
The unit cell diode temperature sensor layout results in considerable flexibility in an array configuration. No matter how the unit cells are arrayed, there is always a diode on a diagonal corner, a diode near the center of one side of the array, and a diode near the physical center of the array. Any array diode may be connected in 4-wire Kelvin configuration using array periphery wire-bond pads.
This cell design and wafer fabrication also allows for creation of extreme non-square arrays. For example, a 1×10 array, approximately 2.5×28mm, might be used to produce heating loads during thermal tests on linear light-source packages.
The bumped version of the thermal test chip wafer, in which there is no metallization interconnecting the individual cells, offers even greater flexibility. By using the mounting substrate to implement connection to each unit cells in an array, it is possible to access each heating resistor independently. With connection to the individual temperature sensing diodes in each cell also available at the same time, specific-location temperature measurements can also be made. The total number of heating resistors in any array is 2N (N = number of unit cells) and the corresponding number of temperature sensors is 4N. A 4×4 (approx. 10×10mm) would have 32 resistors and 64 diodes. Similarly, an array used to simulate a microprocessor-sized chip in the range of 25×30mm, would be a 9×11 configuration with 198 resistors and 392 diodes. This provides fine-grain power application and temperature sensing capability and flexibility to allow for power mapping investigations and for study of spot cooling technologies.
Typical applications for the thermal test chip include:
Thermal Test Chips provide another tool for thermal management design, simulation and measurement activities at the package, board, and system levels. The ability to create a specific chip size from an array of uniform, stable and predictable unit cells takes this tool to new levels of versatility.
Contact Bernie Siegal, Thermal Engineering Associates, Inc., firstname.lastname@example.org