by Françoise von Trapp, contributing editor
I've recently discovered that when there's too much to do, it's best to start by making a list. Even if you only accomplish the first item, just putting them all down clears brain space and allows you to get down to business. The TSV limitation check-list has been established for quite some time. We keep writing it down. It looks something like this:
So far, the most progress has been made on the first item. The processes are in place, ready and waiting for the rest of the list to be checked off. In the past week, two of those items are seeing progress: development of EDA tools and high-volume production tools.
This week, a joint announcement was made by Javelin Design Automation, IMEC, and Qualcomm about successful development of a 3D design flow using Javelin's latest generation design tool to determine accurate performance/power/cost estimates for a 3D stack. The flow was then validated by using it in a smart phone application. The results demonstrated how using TSVs as the method of interconnect allows for a decrease in power, thereby allowing for an increase of bus-width between microprocessor and memory.
"The PathFinding results indicate close to 10 times decrease in dynamic interconnect power of the IO interface using 3D interconnect technologies, subsequently allowing the bus-width to increase by 16 times in 3D implementation, without exceeding the power of the original SIP implementation." Said Roger CarpenterCTO of Javelin. "This sample design case shows how TSV technology can remove the bottleneck between processor and memory."
"We believe PathFinding is critical to the success of 3D integration technology and we are excited to work with Javelin in this area." said Luc Van Den Hove COO at IMEC.
Pol Marchal, principal scientist of IMEC who worked on the project said that because 3D system-level decisions greatly impact final cost, physical design prototyping is an essential step in the 3D design flow. In addition to this pathfinding tool. Marchal says design authoring and verification tools should follow in due time. These include 3D place-and-route , layout, layout vs. schematic check / design rule check, etc.
High-volume Production Tools
As the race to develop high-end production tools continues, TNO and BESI/Datacon announced the joint development of an advanced die bonder for high volume 3D die stacking. And next month at SEMICON China, Kulicke & Soffa's die bonder division intends to introduce a die bonder for 3D die stacking. However, the two companies' tools take different approaches in addressing die-stacking challenges.
According to Richard Boulanger, of K&S, current stacking processes involves addressing one die at a time, grind them very thin then adding some form of bump on the bottom of the via so it can be attached to the next. Figure 1 demonstrates this process using gold metallurgy, but solder could also be used. In this example, the vias are around 10µm with a solder bump of 25µm.
K&S's tool will focus on high-performance stacked die applications first but will extend in other markets later. At this writing, there was no further information available about this tool, but I hope to have something more to report by the time SEMICON China rolls around. As K&S has its hand in wire bond and gold ball bumping, I'll be curious to see what method of interconnect this tool will be based on.
TNO, an Eindhoven-based scientific company with an arm in high-end equipment, approached BESI/Datacon as part of its BlueBird project; namely in developing a high-end pick-and place tool for die-to-wafer (D2W) stacking. http://www.tno.nl/content.cfm?context=markten&content=case&laag1=181&item_id=787 The companies say they are confident that this tool will be the production tool of the future for die-to-wafer (D2W) in the emerging market of 3D stacking.
Datacon brings experience in advanced D2W (also called advanced chip-to-wafer) technologies, as they have been collaborating on these processes for quite some time with EV Group. That work resulted in a toolset consisting of a high volume flip chip bonding equipment for a pre-bond process, at which point fully assembled wafers were transferred to a chip-to-wafer bonder for permanent bond. A prototype of the TNO/BESI/Datacon tool is scheduled for introduction by the end of this year, with commercial launch sometime in 2010.
So can we check EDA tools and high-volume equipment off the list? Not quite yet, but it's good to know they're making it to the top and work is clearly under way. I'll keep you posted.
Françoise von Trapp, contributing editor, is following the course of 3D IC packaging on her blog, Françoise in 3D.