One 3D technique has already made it to the market: stacked chips interconnected via the package by means of peripheral wire bonds. This technology allows producing heterogeneously integrated systems with reduced form factors. It also allows stacking 2D chips without extra design costs. But it can only interconnect peripheral IO bond pads, resulting in a limited interconnect density and a limited interconnection speed, due to high inductance appearing on the long wire bonds.
TSVs, albeit via-last TSVs, could replace wirebond-based interconnects. Unlike these, they are not restricted to peripheral bond pad connections. And they can be made smaller, allowing for higher densities of interconnects. Because TSVs directly connect dies and do not have to pass through the package, they are also much shorter and faster.
The technique where 3D interconnects are realized after wafer fabrication at the bondpad interconnect level is 3D WLP. The minimum required density for interconnects is equal to that of the typical chip I/O pad density. Their placement on the die, however, is not necessarily restricted to the periphery, which opens the route to denser 3D interconnects and smarter designs. And because they are typically used on dies with a thickness of 100µm or less, these TSVs are much shorter than wire bonds and show a better electrical performance.
The major challenge to 3D-WLP is to realize cost-effective TSVs without compromising the quality and reliability of the ICs. This is also the focus of the 3D-WLP technology development at IMEC. The technology under development realizes the TSVs starting from the backside of the wafer and connecting to the first metal layer on the die, avoiding the etching through the BEOL on-chip interconnect layers.
Another characteristic is the use of a polymer insulation layer between the TSV metallization and the silicon. This differentiates the process from most other approaches in which via isolation is realized using CVD-oxinitride layers typically between 50 and 150nm. The use of such thin oxide leads to a high capacitance values for the TSV. Using a thick polymer significantly reduces the capacitance, improving the electrical performance. A further advantage of using a thick polymer is that it can absorb some of the stress induced by the CTE mismatch between the Cu in the via and the surrounding Si. Also, the process flow has been optimized to require only lithography on the wafer surface, not in the via itself.
A typical flow consists of first mounting the wafer on a carrier followed by thinning the wafer to about 50 µm. Next, a 5µm wide annular ring – the so-called "donut" – is DRIE etched from the backside of the wafer to the frontside IC PMD layer. Then the annular ring is filled with a polymer. A second lithography step exposes the central part of the TSV, allowing a selective etch of the remaining Si in the via. At the bottom of this via, the frontside PMD isolation layer is etched away to expose the first metal layer. In the next step, this metal is connected by the sputtered seed-layer deposition and the Cu metal plating. For large via diameters, and to reduce the plating cost, vias can be metalized conformally. For smaller via diameters, a bottom-up via fill is preferred. Finally, dies are bonded backside to topside with micro-bumps.
One of the advantages of this process is that established wafer-level packaging infrastructure and techniques (such as microbumping) are used. Also, the processing is independent of FEOL and BEOL processes, making it possible to outsource the TSV process to a packaging and assembly house.
These advantages come at a cost. 3D WLP TSVs are mainly used for bondpad type of connections; the vias cannot be made dense and small enough for connecting deeper circuit levels. Further, the thermal budget of the process should be kept low for post IC process compatibility.
Some of the process issues that need further attention are the via metallization process which takes rather long for bottom-up fill and CTE mismatch between the Si and the Cu in the vias, where a large Cu TSV plug in large diameter TSVs may cause significant thermo-mechanical stress.
Some further challenges for 3D via processing
Next to the technological challenges of TSV processing, some other considerations are equally important to make 3D chips with TSVs an established industrial technology. Foremost, the technological complexity has to be minimized to allow for high process yields and to make the process economically viable. Related, the stacking technique must optimize the compound yield, e.g. allowing further processing of only known-good-dies through testing at different stages in the process flow. In addition, the chips should be designed so that they can fully benefit from the new capabilities of 3D-stacking technologies.