By Paul A. Magill, Ph.D., Nextreme Thermal Solutions, Inc.
Electrical latency issues are set to become the limiting factor in obtaining higher processor speeds as the line sizes of the devices themselves continue to shrink. The electronics industry is moving to 3D packaging structures which will shorten the electrical path length, thereby allowing for higher transmission speeds. Of course, as this clears the way for faster processors, it also means that thermal management solutions for these 3D structures will also need to be developed. Cooling solutions will likely need to be integrated in a seamless manner into the existing packaging infrastructure.

Flip chip, a method for interconnecting semiconductor devices to external circuitry, makes use of solder bump arrays that have been deposited onto the chip pads. The flip chip bumping process is one such process that could be investigated for integrating thermal management. In fact, these solder bump structures are sometimes considered for passive removal of heat. They also offer an opportunity to integrate active thermal functionality due to their close proximity to the heat source using thin-film thermoelectric technology. Here we propose to integrate thermally active thin-film material directly into a flip-chip solder bump, in essence, creating a thermally active solder bump.

Core to this new thermal management paradigm is the development of the thermal copper pillar bump, also referred to as the "thermal bump." The thermal bump is a thermoelectric structure made using a thin-film material that is embedded into flip-chip interconnects (for this discussion, copper pillar solder bumps) for use in electronic packaging. Thin-film thermoelectric materials may be grown using a metalorganic chemical vapor deposition (MOCVD) reactor in layers ranging from fractions of a nanometer to several microns in thickness. The thermal bump makes use of the Peltier effect. For each bump, thermoelectric cooling occurs when a DC current is passed through the bump. The thermal bump pulls heat from one side of the device and transfers it to the other as current is passed through the material.

Figure 1: 100µm high thermal bumps arrayed during the manufacturing process
The thermal bump is a method for integrating active thermal management functionality at the chip level in the same manner that transistors, resistors, and capacitors are integrated in conventional circuit designs today. Unlike conventional solder bumps that provide an electrical path and a mechanical connection to the package, thermal bumps act as solid-state heat pumps and add thermal management functionality locally on the surface of a semiconductor chip or other electrical component.

The use of thermal bumps for cooling of 3D electronics offers many advantages in terms of size, efficiency, and power-pumping capability. The bump adds as little as 100100µm of thickness to a heat spreader, enabling unobtrusive integration close to the heat source. Thermal bumps have been shown to achieve a temperature differential of 60°C between the top and bottom headers, and have demonstrated power pumping capabilities exceeding 150 W/cm². This makes thermal bumps ideally suited for applications involving high heat-flux flows. The size advantage of the thermal bump further enhances the integration of thermal management capabilities at the wafer, die, or package levels.

Thermal Bumps in 3D Cooling Applications
Combining thermal bumps with a 3D chip stack structure will lead to thermal management solutions that are also 3D by nature. Figure 2 illustrates the thermal management concept. By extending the only currently available option of passive back-side cooling to also include back and front-side, as well as lateral heat removal in an active manner, thermal management of the 3D stack may be significantly enhanced.

Figure 2: 3D thermal management

Back-side Cooling
Back-side cooling can be enhanced by the introduction of thermal bumps either into the heatsink to form an active heatsink or into the heat spreader. Figure 3 illustrates this approach. Here, discrete devices are used to mitigate hot spots generated on the front side of a die. The following example demonstrates the feasibility of hot spot cooling using integrated thermoelectrics.

Figure 3:Back-side cooling.

For this example the hotspot is on the active side of the die while the thermoelectric device is attached to the copper heat spreader. In future implementations it could be envisioned that the thermoelectric material would be embedded on the back side of the die at the through-silicon-via (TSV). The heat spreader is flipped onto the backside of the die so that the thermoelectric device is located near the backside of the die, behind the first-level thermal interface material, or TIM1.

In this specific example, the entire chip was dissipating 62 W, with 2 W generated by the hot spot, resulting in a hot-spot heat flux of 1,250 W/cm². The baseline temperature in the area of the hot spot without the TEC is about 111°C. In this example, the integrated thin-film cooler reduced the hot spot temperature by up to 14°C.

Lateral Cooling
Figure 4 illustrates the concept and implementation in practice for lateral heat removal. Here, the current flows from left to right, but the heat flows from the center of the module outwards.

Figure 4:Lateral cooling.

For a 3D chip stack, this lateral heat removal concept can be combined with an interposer through which the heat can be removed. Here, the thermoelectric material is underneath the substrate and the heat is pulled from the center segment to the side. Therefore, the center of the platform will be cool and the sides will be hotter as shown. With this approach, heat is dissipated laterally to the walls.

Active-side Cooling
The last approach shown is for active-side cooling. In Figure 5, an artist's rendition depicts the active side of a microprocessor. The smaller structures represent conventional copper pillar bumps next to the larger thermal bump. There could be as few as 10 -20 or as many as 600 -1200 thermal bumps strategically placed on the chip but only in the vicinity of the hot spots. By doing so, it is not necessary to use a large amount of thermoelectric material – as little as 1mm x 1mm per hot spot – to achieve the desired cooling effect and with a higher efficiency.

Figure 5: Thermal and electrical bumps integrated on a single substrate.

Figure 6 shows a complete 3D thermal management solution made possible by the introduction of thermal bumps.

Figure 6: Integrated 3D thermal management.

Summary
The thermal bump and its implementation in three methods for 3D cooling — back-side, active-side and lateral cooling — opens the door to a new generation of electronic product design by bringing chip and module-level thermal management directly into the packaging process. In the same manner that shrinking the silicon line and die sizes have made electronic products ubiquitous in our daily lives, so will shrinking the physical scale of thermal management materials. Integrating thermoelectric materials into the interconnect structure, instead of as device add-ons, enables chip-level thermal management for traditional and 3D products.

Paul Magill, Ph.D.,VP of marketing and business development, may be contacted at Nextreme Thermal Solutions, 3908 Patriot Drive Suite 140, Durham, NC 27703; 919-597-7300; E-mail: pmagill@nextreme.com